In power MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) application, resistance and thermal performance are two very important parameters. To improve the resistance and the thermal performance, a thin die is used in the semiconductor devices and the source or the drain of the FET (Filed Effect Transistor) is exposed. However, as a semiconductor wafer is ground to below 200 microns, it is likely to be cracked during grinding and in the subsequent cutting and packaging process. It is therefore necessary to develop a new packaging process to obtain a semiconductor package with low resistance and high heat dissipation.